library ieee;
use ieee.std_logic_1164.all;

package mis_componentes is

component pract1 is
port(A,B,C,D,E:in std_logic;
	I:out std_logic);
end component;

component pract2 is
port(A,B,C,D,E:in std_logic;
	F:out std_logic);
end component;


component pract3 is
port(A,B,C,D :in std_logic;
	G:out std_logic);
end component;


component pract4 is
port(A,B,C,D :in std_logic;
	H:out std_logic);
end component;

end mis_componentes;